This invention relates to configurable integrated circuit devices, and, more particularly, to efficient rounding circuits and methods in specialized processing blocks which may be included in such devices.
Considering a programmable logic device (PLD) as one example of a configurable integrated circuit device, as applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.
For example, PLDs sold by Altera Corporation, of San Jose, Calif., as part of the STRATIX® family include DSP blocks, each of which includes a plurality of multipliers. Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components of the block to be configured in different ways. In each such block, the multipliers can be configured not only individual multipliers, but also as one larger multiplier. In addition, one complex multiplication (which decomposes into two multiplication operations for each of the real and imaginary parts) can be performed. The aforementioned adder can be used for the aforementioned accumulation function by feeding back the adder output to its input via a multiplexer that can choose to use or not use that feedback input.
The operations performed by such DSP blocks frequently require rounding. However, known rounding implementations have required the addition of circuitry to the DSP blocks.